Restructuring WSI hexagonal processor arrays

نویسندگان

  • Raja Venkateswaran
  • Pinaki Mazumder
  • K. G. Shin
چکیده

Fault-tolerant approaches have been widcly em­ ployed to improve the yield of ULSI and WSI processor arrays. In this paper, we propose a host-driven reconfiguration scheme, called HEX-REPAIR, for hexagonal processor arrays charac­ terized by a large number of relatively simple cells. Such arrays have heen shown to be the most efficient for many digital signal processing applications, such as matrix multiplication, and for some classes of filtering operations. Reconfiguration for these arrays is made difficult by the asymmetric nature of the inter­ connection network and the need for keeping the switching overheads at a minimum. The algorithm presented in this pa­ per meets these requirements. In addition, it has excellent fault­ coverage characteristics, even in the presence of multiple faults, and can accommodate multiple rows/columns of spare cells. The restructured array is transparent to users and no modification is required in any application program using the array.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Integrated Diagnosis and Reconfiguration Process for Defect Tolerant WSI Processor Arrays

This paper presents a new technique for construchg a fault-free subarray from a defective WSI (wafer scale integration) processor array based on an integrated diagnosis and reconfiguration (IDAR) method. In a traditional yield enhancement approach, it diagnoses all units first and then the status (faulty or fault-free) of all units are passed to the reconfiguration algorithm for a possible reco...

متن کامل

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its s...

متن کامل

Restructuring Arrays for E cient Parallel Loop

In a sequential program, data are often structured in a way that is optimized for a sequential execution. However, when the program is parallelized, the data access pattern may change drastically. If the structure of the data is not changed accordingly, parallel performance will su er. In this paper, we consider this problem in the context of runtime loop parallelization [8, 9], which is a gene...

متن کامل

Restructuring Arrays for E cient Parallel Loop Execution

In a sequential program, data are often structured in a way that is optimized for a sequential execution. However, when the program is parallelized, the data access pattern may change drastically. If the structure of the data is not changed accordingly, parallel performance will su er. In this paper, we consider this problem in the context of runtime loop parallelization [8, 9], which is a gene...

متن کامل

A RAM-based Neural Network Architecture for Wafer Scale Integration

While the use of WSI technology to increase the integration density of RAM devices may not be cost effective (cf. Anamartic’s failed WSI RAMs [23]), low defect tolerance overheads, high testability, and low power consumption make memories ideal building blocks for WSI processor architectures. Indeed, this is reflected in the number of memory-based WSI devices manufactured to date [15,19,22,23,24].

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • IEEE Trans. on CAD of Integrated Circuits and Systems

دوره 11  شماره 

صفحات  -

تاریخ انتشار 1992